1. Field of the Invention
The present invention generally relates to a microcomputer, and more specifically to a microcomputer having a central processing unit, and a watchdog timer generating a non-maskable interrupt in response to an overflow of the timer.
2. Description of the Prior Art
Conventionally, many microcomputers include a central processing unit (CPU), an interrupt controller (INTC), and peripheral circuits such as an analog-to-digital (A/D) converter and a serial transfer circuit, all of which are manufactured in a single semiconductor chip. Also, many microcomputers include a watchdog timer (WDT) which generates a non-maskable interrupt in response to an overflow of the timer in order to improve the reliability of the microcomputer system.
When a watchdog timer is used, a program for clearing (or presetting) a counter of the watchdog timer within a predetermined time period is executed, so that if the program executed without trouble, no overflow of the watchdog timer is generated. For example, at a time of program runaway, if the counter of the watchdog timer is not preset because of occurrence of an anomaly even after the predetermined time period has elapsed, an overflow occurs in the watchdog timer. This overflow is detected as a non-maskable interrupt, and a notice of a system abnormality is transmitted to an external device and program operation is branched to a previously programmed routine, such as a reset routine for performing processing for the anomaly occurrence.
As mentioned above, the WDT (watchdog timer) interrupt cannot be masked by an external interrupt (El) flag or the like, in contrast to ordinary maskable interrupts. Therefore, when another interrupt processing routine is under execution, if the WDT interrupt occurs, the operation is branched to the WDT interrupt processing routine. Accordingly, when it is necessary to prepare a program which is generated and processed asynchronously from an execution condition of an internal program, similarly to an interrupt processing routine for processing an interrupt request from an external device, there is a possibility that the counter of the watchdog timer cannot be preset within the predetermined time period. Therefore, in order to preventing the WDT interrupt from occurring because the situation is misunderstood as being a system abnormality, the WDT preset instruction is executed at a beginning of the interrupt processing routine.
Also in the case that it is desired to complete an interrupt processing routine in the shortest time, as in an application system for detecting from an external interrupt (EI) that the supply of an electric power to the system is stopped, and executing a saving of control data and change of port outputs, the WDT preset instruction is executed at a beginning of the interrupt processing routine in order to avoid wasted time due to the occurrence of the WDT interrupt.
In order to make it possible to execute the WDT preset instruction at a beginning of the interrupt processing routine, the CPU does not receive an interrupt request from the interrupt controller just after the operation is branched to the interrupt processing routine. As a result, an instruction at a heading address of the interrupt processing routine is executed without exception. On the other hand, the interrupt controller performs receipt of interrupt processing requests and a priority level control, and notifies the CPU of the occurrence of interrupt request. When a plurality of interrupt processing requests are in conflict, this interrupt controller is configured to process the first request, in order of occurrence, and to retain later occurring request(s). Therefore, when an external interrupt (El) request occurs and is transferred from the interrupt controller to the CPU, if the WDT interrupt processing request occurs in a period in which the CPU is executing the branch processing going to the external terminal interrupt processing routine, the CPU first branches to the external terminal interrupt processing routine so as to execute the heading instruction thereof, and thereafter, branches to the WDT interrupt processing routine.
Although the watchdog timer presetting is executed at the beginning of the interrupt processing routine, if the overflow occurs in the watchdog timer, there is the possibility that during the execution of the external terminal interrupt processing, the operation is branched to the WDT interrupt processing routine by the WDT interrupt processing request. In the conventional microcomputer, when the WDT interrupt and another interrupt are in conflict, even if the WDT presetting instruction is executed at a beginning of the first branched interrupt processing routine, the overflow occurs in the watchdog timer, and the operation is branched to the WDT interrupt processing routine by the WDT interrupt processing request. Therefore, in the case in which it is desired to complete an interrupt processing routine in a short time, as in an application system for detecting from an external interrupt (EI) that the supply of an electric power to the system is stopped and executing a saving of control data and change of port outputs, when the WDT interrupt processing routine performs the branch to the reset routine, the processing for the electric power-off is not executed.
On the other hand, in the case that the WDT interrupt processing routine does not perform the branch to the reset routine and the operation is returned to the first branched interrupt processing routine after the WDT interrupt processing has been completed, since it is necessary to design the system by previously calculating the processing time of the WDT interrupt as wasted time, an additional circuit for maintaining the electric power supply to the microcomputer during a predetermined period of time after the power-off of the main electric power supply to the application system is required to have a larger electric power supply capacity. This solution adds expense to the system.